This invention relates to semiconductor devices which are supplied at signal levels at various EMF (electromotive force) levels or potentials, usually referred to as "voltage levels". These voltage levels typically include a ground or substrate potential V.sub.SS and a signal level potential V.sub.CC. The device is usually driven by current supplied at V.sub.CC to V.sub.SS.
CMOS technologies, with their low static power consumption and high speed, has become the technology of choice for almost all VLSI applications. Because it employs both p-channel and N-channel MOS transistors, parasitic NPN and PNP bipolar transistors are formed. Together they form the PNPN layer which is commonly known as the silicon-controlled rectifier (SCR); they stay on once they have been turned on. This mode is known as "latch-up" and can be self-destructive because excessive currents can flow through the junctions. The reduction in dimensions further accentuates this parasitic component responsible for a self-destructive mode.
In order to model latch-up, it is convenient to use the four-layer configuration as two coupled transistors, shown in FIG. 1. As illustrated in FIG. 1A, a p+ source/drain and a P substrate form the emitter and collector regions of a vertical PNP transistor, schematically shown as Q1. An N+ source/drain and an n-well form a lateral NPN transistor, schematically shown as Q2. The parasitic vertical PNP and lateral NPN bipolar transistors Q1, Q2 can introduce latch-up if either of the base-emitter junctions becomes forward biased. The parasitics can be described as a four layer P+NPN+ diode called a silicon-controlled rectifier (SCR). The SCR's operation depends on an internal feedback mechanism triggered by operating voltage above V.sub.CC or below ground; by internal thresholds; by radiation-induced currents or by photo excitation.
The most common cause is due to voltage overshoot and undershoot at the input and output terminals (voltage "bumping") with respect to the anode voltage and the ground potential, respectively. The effects of voltage "bumping" to lower potentials is of primary concern in this invention.
A p-channel device will latch up when its source or drain is forced above V.sub.CC with a charge current, called the trigger current. This current causes Q1 to become forward biased and to turn on. Referring to FIG. 1B, Q1's collector current, IC1, now feeds with the base of Q2 (IB2) and the parasitic resistor R2. Since R2 pulls base current from Q2, it causes a voltage appear at Q2's base. When this potential reaches the range of 0.6 to 0.7 volts (1NPN.times.R2), Q2 turns on and begins to feed current into R1 and Q1's base. This latch-up loop will continue until voltage is removed or the circuit self destructs.
An n-channel device will latch up when its source or drain voltage is forced below V.sub.SS and a similar process begins at Q2. The current required to initiate latch-up can be expressed in terms of the fundamental transistor parameter alpha (.varies.). The variation of alpha is a fundamental feature of the SCR.
Ignoring for the moment the resistive paths, then from bipolar circuit theory, the collector currents flowing into Q1 and Q2 are given as: EQU I.sub.C1 =.varies..sub.p I.sub.E -I.sub.C01 EQU I.sub.C2 =.varies..sub.n I.sub.E +I.sub.C02
where the Ic0 are the collector saturation currents. We can set the sum of the currents flowing into Q1 equal to 0 to show that EQU I.sub.E +I.sub.C1 -I.sub.C2 =0 EQU I.sub.E =I.sub.C1 -I.sub.C2 =0
by substituting the expressions for the collector currents, we get ##EQU1##
This equation predicts that as the sum of the transistor alphas approaches unity, the current increases rapidly. The circuit will latch up if the current gains are large enough that the sum (.varies.n+.varies.p) is equal or greater than 1. (The terminal current does not increase indefinitely; as the sum of the alphas approaches unity, this simplified analysis breaks down.)
Reducing the susceptibility to latch-up can therefore be accomplished by processing techniques that reduce resistances.
FIG. 2 shows a prior art configuration of I/O lines 11, 12 on a semiconductor, in which the I/O lines are precharged to a voltage V.sub.CC in order to permit signal sensing. The I/O lines 11, 12 include sense line portions 15, 16 and external connection portions 17, 18. The precharging is done by gating on precharge transistors Q1, Q2 with an equalization signal EQU, in order to bring the sense line portions 15, 16 of the I/O lines to V.sub.CC. The equalization signal EQU is also used to gate on a balance transister Q3, which effects conduction between the sense line portions 15, 16 of the I/O lines 11, 12. The precharge transistors Q1, Q2 (and Q3) are p-channel transistors. Transistors Q1-Q3 are gated off after a precharge period, causing the sense line portions 15, 16 to float.
If sense line portion 15 and 16 of the I/O lines 11, 12 remain isolated from external connection portions 17 and 18, then the I/O lines will float at V.sub.CC.
In a present configuration, when V.sub.CC is at 6 volts, then sense line portions 15, 16 are floated at 6 volts. If V.sub.CC then "bumps", for example, to 5 volts (V.sub.CC -1V), sense line portions 15, 16 exceed V.sub.CC, by 0.7 volts, resulting in a forward bias of Q1 and Q2 wells of the 0.7 volts. Since Q1 and Q2 are p-channel transistors, the forward bias of P+ drain and an N- well results in a potential latch-up condition. Because current flows, the forward bias also results in a reduction in sense signal strength.
The precharge transistors Q1 and Q2, and particularly the balance transistor Q3 are vulnerable to V.sub.CC "bumping" down to a lower potential than a precharge voltage of the I/O lines 11, 12, once the I/O lines are floated.